Referring to FIG. 1 a final sum is calculated according to a formula A*C+B, with an addend 20, a multiplicand 21 and a multiplier 22, wherein A, B and C each have a fraction and an exponent part, and the exponent of the product A*C, calculated by multiplier 23, is calculated and compared to the exponent of the addend 20 under inclusion of an exponent bias value dedicated to use unsigned biased exponents. The comparison yields a shift amount denoted herein as SA, which is used for aligning the addend 20 with the product operand 24 in order to build the final sum. Exemplary prior art is given by U.S. Pat. No. 5,166,898 incorporated herein by reference.
With reference to FIG. 1 the prior art provides an arithmetic unit designed to be operable in two distinct operation modes, in which the A, B, C operands 20, 21, 22, respectively, are represented in their totality in a respective specific type of floating point format, for instance, wherein all operands have either a binary IEEE-compliant representation, or all operands having a hexadecimal representation, which is fabricated by the applicant in the prior art arithmetic processors of the IBM z/Series and of IBM S/390, which can be found e.g. in proceedings of 16th IEEE Symposium on Computer Arithmetic, ARITH-16, June 2003 in article “High Performance Floating-Point Unit with 116 bit wide Divider” ISBN 0-7695-1894-x ISSN 1063-6889 incorporated herein by reference.
Other prior art arithmetic units also offer a dual mode operation, wherein all operands have either a binary IEEE-compliant representation, or all operands have a different—e.g., an octal—representation.
It should be noted that no mixed mode operation, wherein one operand is binary for example, and the other two are hexadecimal, is the subject of the present invention.
In the prior art defined by arithmetic units of the applicant in the IBM z-series and in IBM S/390, the shift amount SA is calculated as follows:SA=expA+expC−bias−expB+constant=expA+expC−expB−constant2 (constant2=bias−constant)
The constant is needed to compensate for an eventual shift left of the addend before adding product and addend operand.
Disadvantageously, hexadecimal and binary formats have different bias values; therefore the constant2 value is different for hexadecimal and binary, see logic 25A for binary and 25B for hexadecimal:
IEEE 754 standard notations (s:=sign, f:=fraction):
    Binary Single=(−1)**S*1.F*2**(exp−127)    Binary Double=(−1)**S*1.F*2**(exp−1023)    Binary Quad=(−1)**S*1.F*2**(exp−16383)
It should be noted that the binary bias is of the form (2**(N−1))−1.
IBM S/390 hexadecimal notation:Hexadecimal=(−1)**S*0.F*16**(exp−64)It should be noted that the hex bias is of the form (2**(N−1)).
With respect to further increased clock rates the above shift amount calculation is very timing critical because it is used to align the addend into a very wide dataflow. In prior art implementations of the above-mentioned z-series, either two different constant values are multiplexed in a multiplexer 26 in front of a 4-port adder, or two 4-port adders are used to calculate both shift amount values, wherein the correct value for the particular operational mode (e.g. binary or hexadecimal) is selected later on.
The above-mentioned first option has an increased delay since the select signal must drive an exponent width multiplexer (for example a 13-bit multiplexer for a 64-bit dataflow) in order to select the constant, whereas the second option needs more hardware and still adds a multiplexer stage to the critical path.
Disadvantageously, both prior art alternatives are too slow for offering a further increased cycle rate required for new processor designs.